abs = 16 bit absolute address # = 8 bit immediate value impl = nothing (register changes are implied) A,X,Y = implied register usage of AC, XR, YR rel = signed 8bit immediate for branching (relative to current PC) zpg = zeropage op l syntax ---------------------------- 00 1 BRK impl 01 ORA X,ind 05 ORA zpg 06 ASL zpg 08 1 PHP impl 09 ORA # 0A ASL A 0D ORA abs 0E ASL abs 10 BPL rel 11 ORA ind,Y 15 ORA zpg,X 16 ASL zpg,X 18 1 CLC impl clear SR.C 19 3 ORA abs,Y 1D 3 ORA abs,X 1E 3 ASL abs,X 20 3 JSR abs push PC+2, PC = abs 21 AND X,ind 24 BIT zpg 25 AND zpg 26 ROL zpg 28 1 PLP impl 29 2 AND # AC = AC AND # 2A ROL A 2C BIT abs 2D AND abs 2E ROL abs 30 BMI rel 31 AND ind,Y 35 AND zpg,X 36 ROL zpg,X 38 1 SEC impl set SR.C 39 AND abs,Y 3D AND abs,X 3E ROL abs,X 40 1 RTI impl 41 EOR X,ind 45 EOR zpg 46 LSR zpg 48 1 PHA impl 49 EOR # 4A LSR A 4C JMP abs 4D EOR abs 4E LSR abs 50 BVC rel 51 EOR ind,Y 55 EOR zpg,X 56 LSR zpg,X 58 1 CLI impl clear CL.I 59 EOR abs,Y 5D EOR abs,X 5E LSR abs,X 60 1 RTS impl 61 ADC X,ind 65 ADC zpg 66 ROR zpg 68 1 PLA impl 69 ADC # 6A ROR A 6C JMP ind 6D ADC abs 6E ROR abs 70 BVS rel 71 ADC ind,Y 75 ADC zpg,X 76 ROR zpg,X 78 1 SEI impl set SR.I 79 ADC abs,Y 7D ADC abs,X 7E ROR abs,X 81 STA X,ind 84 STY zpg 85 STA zpg 86 STX zpg 88 1 DEY impl 8A 1 TXA impl AC = XR 8C STY abs 8D STA abs store AC at abs address 8E STX abs 90 BCC rel 91 STA ind,Y 94 STY zpg,X 95 STA zpg,X 96 STX zpg,Y 98 1 TYA impl 99 STA abs,Y 9A 1 TXS impl 9D 3 STA abs,X (abs address + XR) = AC A0 2 LDY # YR = # A1 LDA X,ind A2 2 LDX # XR = # A4 LDY zpg A5 LDA zpg A6 LDX zpg A8 1 TAY impl YR = AC A9 2 LDA # AC = # AA 1 TAX impl XR = AC AC LDY abs AD LDA abs AE LDX abs B0 BCS rel B1 LDA ind,Y B4 LDY zpg,X B5 LDA zpg,X B6 LDX zpg,Y B8 1 CLV impl B9 LDA abs,Y BA 1 TSX impl BC LDY abs,X BD LDA abs,X BE LDX abs,Y C0 1 CPY # C1 CMP X,ind C4 CPY zpg C5 CMP zpg C6 DEC zpg C8 1 INY impl C9 CMP # CA 1 DEX impl CC 3 CPY abs CD 3 CMP abs CE 3 DEC abs D0 BNE rel D1 CMP ind,Y D5 CMP zpg,X D6 DEC zpg,X D8 1 CLD impl clear SR.D D9 CMP abs,Y DD CMP abs,X DE DEC abs,X E0 CPX # compare XR with 8bit immediate (Sets RS.C if XR >= #, RS.Z if XR = #) E1 SBC X,ind E4 CPX zpg E5 SBC zpg E6 INC zpg E8 1 INX impl E9 SBC # EA 1 NOP impl EC CPX abs compare XR with 8bit at 16 bit [abs] address ED SBC abs EE INC abs increment 8bit value at [abs] address by one F0 BEQ rel F1 SBC ind,Y F5 SBC zpg,X F6 INC zpg,X F8 1 SED impl set SR.D F9 3 SBC abs,Y FD 3 SBC abs,X FE 3 INC abs,X ------------------ src http://e-tradition.net/bytes/6502/6502_instruction_set.html